Phase-locked loop (PLL) integrated circuits are frequently used to generate clock signals for synchronous integrated circuit systems. As will be understood by those skilled in the art, PLL integrated circuits may multiply a reference clock frequency by some number to thereby generate a relatively high frequency clock. This multiplying number can be a fractional number if fractional dividers are utilized in a feedback loop of the PLL. One typical technique to implement a fractional divider is to utilize a multi-modulus divider (MMD) with a delta-sigma modulator (DSM), which outputs a sequence of integer numbers having a fractional average value. The MMD uses these integer numbers as divisors. For example, these integer numbers can be any one of [N1, N2], where N1 and N2 are determined by the desired fractional number and the DSM order. To achieve proper operation, there should be no delays or intermediate divisors of the MMD. One example of fractional divider is disclosed in commonly assigned U.S. application Ser. No. 13/425,761, filed Mar. 21, 2012, entitled “Fractional-N Dividers Having Divider Modulation Circuits Therein with Segmented Accumulators,” the disclosure of which is hereby incorporated herein by reference.
An example of a programmable MMD with extended range is disclosed in an article by Cicero S. Vaucher et al., entitled “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology,” IEEE JSSC, Vol. 35, No. 7, July 2000. A shown by FIGS. 1-2, a portion of this MMD 100 includes several stages of div2/3 cells 110 and logic circuits (e.g, OR gates, inverters). Each div2/3 cell includes four (4) level-sensitive D-type latches and three (3) AND gates, connected as illustrated. When signal MODin=1 and signal P=1, a divide-by-3 function is realized so that the states 201, 202 change as follows: (0,1)→(1,1)→(0,1). In addition, when signal MODin=0 and signal P=X (i.e., X=0 or 1), a divide-by-2 function is realized so that the states 201, 202 of corresponding D-type latches change as follows: (0,1)→(1,1)→(0,1). Thus, when node 201 is logic 1, MODout repeats the value of MODin and when node 201 is logic 0, MODout is logic 0, with the latch states changing at negative edges of signal Fin. As shown by FIG. 1, each stage of div2/3 cells samples its own MODin and generates its own MODout, with the rightmost input MODin being set high to a logic “1” value. Based on this configuration, each MODout signal is a positive pulse with the pulse width being one period of its own Fin. During this period, each stage has one chance to perform a “check”, when its MODin is high, to determine whether it is supposed to function as a divide-by-3 cell or a divide-by-2 cell depending on its input P. The period of Fout (i.e., Tout) is related to the period of Fin (i.e., Tin) as follows:Tout=Tin(P<0>+P<1>21+ . . . +P<n−1>2n−1+P<n>2n),which means the divisor is equivalent to the binary number P<n:0>(2≦P<n:0>≦2n+1−1). Unfortunately, one problem with the MMD of FIGS. 1-2 is that when a new P<n:0> is loaded, the divisor does not directly change to the new divisor, but can get an uncertain intermediate value before becoming the new value. This property of the MMD of FIGS. 1-2 is not acceptable for fractional divider applications where any discrepancy will result in an error division ratio. U.S. Pat. No. 6,760,397 to Wu et al. and U.S. Pat. No. 6,501,816 to Kouznetsov et al. also disclose efforts to develop multi-modulus dividers for programmable frequency divider and fractional-N divider applications.